Apparatuses and methods for exiting low power states in memory devices
AssigneeMicron Technology, Inc.
InventorsRajesh Sundaram, William Low, Sowmiya Jayachandran
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Abstract
According to one embodiment, an apparatus is disclosed. The apparatus includes a memory device having a device identification. The apparatus further includes a low power wake circuit configured to receive a low power wake signal and an identification information, and further configured to initiate a transition of the memory device from a low power state to an active state responsive to an active low power wake signal and the wake identification information matching the device identifier.
Claims20
An apparatus comprising:
- a memory device having a device identification;
- and
- a low power wake circuit configured to receive a low power wake signal via a first bus, and to receive identification information via a second bus and further configured to initiate a transition of the memory device from a low power state to an active state responsive to an active low power wake signal and the identification information matching the device identification,
- wherein the memory device is configured to receive a chip select signal, the chip select signal configured to enable the low power wake circuit to receive the identification information via the second bus.
The apparatus of claim 3, wherein the memory device is further configured to receive a chip select signal, the chip select signal configured to enable the low power wake circuit to receive the identification information via the command/address bus.
A system comprising:
- a plurality of memory devices, each memory device of the plurality of memory devices associated with respective device identification information and configured to have at least one low power state and at least one active state;
- and
- a command bus coupled the plurality of memory devices and configured to provide wake identification information,
- wherein each memory device of the plurality of memory devices are configured to receive a chip select signal, the chip select signal configured to transition from a low power state to an active state responsive to an active wake signal and the wake identification information matching the respective device identification information, and to remain in the low power state responsive to the active wake signal and the wake identification information not matching the respective device identification information.
A method comprising:
- receiving, by a memory device having a device identification information, an enabling a provided by a first bus;
- providing, by a memory controller circuit, a low power wake identification signal to a second bus;
- receiving, by the memory device, a first command provided by the second bus to enter a low power state;
- prompting, by the activated low power wake signal provided by a low power wake bus, the memory device to determine whether the device identification information matches the low power wake identification signal;
- responsive to determining the device identification information matching the low power wake identification signal, the memory device exits a low power state and enters an active state, allowing the memory device to receive commands to perform memory operations.
Dependencies are inferred from the claim text.