Radar hardware accelerator

A radar sub-system, comprising:

• a split accelerator local memory including ADC input buffers (ADC buffers) for storing radar data sample streams, and output buffers,
• a radar hardware accelerator (HWA) coupled to said ADC buffers for receiving said radar data sample streams and for processing said radar data sample streams, said HWA including:
• a fast Fourier transform (FFT) engine including:
• a pre-processing block for providing at least one of interference mitigation, finite impulse response (FIR) filtering and multiplying said radar data sample streams by a pre-programmed complex scalar or a specified sample from an internal look-up table (LUT) to generate pre-processed samples;
• a windowing plus FFT block (windowed FFT block) for multiplying said pre-processed samples by a window vector and then processing by an FFT block for performing a FFT to generate Fourier transformed samples, and
• a post-processing block for computing a magnitude of said Fourier transformed samples for generating post-processed radar data;
• wherein said pre-processing block, said windowed FFT block, and said post-processing block are connected in one streaming series data path,
• wherein an output of said post-processing block is coupled to an input of said output buffers for transferring said post-processed radar data to said output buffers, and
• a parameter-set configuration memory coupled to a state machine both coupled by a bus to said FFT engine for sequencing parameters sets for execution of a chained sequence of operations and data transfers between said accelerator local memory and an external memory for controlling said pre-processing block, said windowed FFT block and said post-processing block.

A method of (FMCW) radar signal processing using a radar hardware accelerator (HWA), comprising:

• coupling radar data sample streams from ADC input buffers (ADC buffers) to said HWA comprising a fast Fourier transform (FFT) engine for receiving and processing said radar data sample streams including calculating including at least one of interference-thresholding, windowing and range FFT to generate post-processed radar data including range FFT data;
• streaming said post-processed radar data to output buffers;
• transferring said range FFT data from said output buffers to an external memory via direct memory accesses (DMA), said DMA being triggered automatically by said HWA;
• repeating said coupling, said calculating, said streaming, and said transferring for said radar data sample streams received by multiple antennas and across multiple chirps;
• wherein further processing is performed on said range FFT data originating from said multiple antennas and across said multiple chirps, comprising:
• transferring from said external memory in blocks to said output buffers, each said block including data for a first range gate and at least a second range gate;
• performing multiple doppler FFT's using said HWA corresponding to said first range gate, wherein said doppler FFT's are computed for each of said multiple antennas in said first range gate;
• performing an absolute value operation on result of said doppler FFT's for each of said multiple antennas corresponding to said first range gate, and summing results of the said absolute value operation across said multiple antennas, and
• repeating said further processing on subsequent data blocks from said data blocks corresponding to at least said second range gate.