Portion isolation architecture for chip isolation test

A processing system of providing portion isolation design to a chip design having a plurality of portions, comprising:

• a processor;
• and
• a memory storing computer executable instructions, wherein the computer executable instructions comprise:
• a pin group utility module configured to group a plurality of pins of a chip into a plurality of pin groups, and generate a pin group file having the plurality of pin groups, and
• a portion wrapper insertion utility module configured to create a portion boundary wrapper chain, and insert the portion boundary wrapper chain into a chip design file of the chip to facilitate partial-good portion isolation test of the chip.

A computer program product operable on a processing system of providing portion isolation design to a chip design having a plurality of portions, comprising a non-transitory computer storage medium readable by the processing system having a processor and a memory configured to store computer executable instructions for execution by the processor of the processing system for performing a method comprising:

• retrieving a chip design file of a chip, wherein the chip design file comprises pin related information from a chip design database;
• generating, via a pin group utility module, a pin group file according to the pin related information retrieved;
• combining, via a portion wrapper insertion utility module, the pin group file with one or more portion netlists to form one or more localized portion wrapper segments;
• stitching, via the portion wrapper insertion utility module, the one or more localized portion wrapper segments to form a portion boundary wrapper chain;
• and
• inserting, via the portion wrapper insertion utility module, the portion boundary wrapper chain into the chip design file of the chip to facilitate partial-good portion isolation test of the chip.