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US 2017/0324425 A1Published application
Embedded parity matrix generator
AssigneeInfineon Technologies AG
InventorHolger Busch
Life of this patent
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Abstract
A circuit, including an embedded parity matrix generator configured to generate a parity matrix for a data word of any data width; an encoder configured to add a redundancy word to the data word based on the parity matrix; a sub-circuit coupled to the encoder, and configured to receive the data word and the redundancy word from the encoder; and a decoder coupled to the sub-circuit, and configured to receive the data word and the redundancy word from the sub-circuit, and to detect any errors in the data word based on the parity matrix.
Claims20
A circuit, comprising:
- an embedded parity matrix generator configured to generate a parity matrix for a data word of any data width;
- an encoder configured to add a redundancy word to the data word based on the parity matrix;
- a sub-circuit coupled to the encoder, and configured to receive the data word and the redundancy word from the encoder;
- and
- a decoder coupled to the sub-circuit, and configured to receive the data word and the redundancy word from the sub-circuit, and to detect any errors in the data word based on the parity matrix.
2 more elements
A method, comprising:
- generating, by an embedded parity matrix generator, a parity matrix for a data word of any data width;
- adding, by an encoder, a redundancy word to the data word based on the parity matrix;
- receiving, by a sub-circuit coupled to the encoder, the data word and the redundancy word from the encoder;
- receiving, by a decoder coupled to the sub-circuit, the data word and the redundancy word from the sub-circuit;
- and
- detecting, by the decoder, any errors in the data word based on the parity matrix.
3 more elements
Dependencies are inferred from the claim text.