US 2017/0323886 A1 · METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE

Abstract

A method of fabricating a semiconductor device includes forming first gate structure and a second gate structure over a core device region of a substrate. The method further includes forming stressors at opposite sides of the first gate structure. The method further includes doping the stressors to form a first source region and a first drain region of a first device. The method further includes doping into the substrate and at opposite sides of the second gate structure to form a second source region and a second drain region of a second device, wherein the first source region, the first drain region, the second source region and the second drain region are of a same conductivity. The first source region includes a different material from the second source region.

Claims20

Dependent claims

A method of fabricating a semiconductor device, the method comprising:

forming first gate structure and a second gate structure over a core device region of a substrate;
forming stressors at opposite sides of the first gate structure;
doping the stressors to form a first source region and a first drain region of a first device;
and
doping into the substrate and at opposite sides of the second gate structure to form a second source region and a second drain region of a second device, wherein the first source region, the first drain region, the second source region and the second drain region are of a same conductivity, and the first source region comprises a different material from the second source region.

2 more elements

Dependencies are inferred from the claim text.

Facts

Application

15/662,541Filed 28 Jul 2017

Priority

12 Feb 2014

Published

9 Nov 2017

Term ends

Not estimatedThe source records don’t support an estimate.

Classification23 codes

H10D 84/83
Of only field-effect components: of only insulated-gate FETs [IGFET]
H10D 30/797
Arrangements for exerting mechanical stress on the crystal lattice of the channel regions: being in source or drain regions, e.g. SiGe source or drain
H10D 62/021
Manufacture or treatment: forming source or drain recesses by etching e.g. recessing by etching and then refilling
H10D 62/822
Heterojunctions: comprising only Group IV materials heterojunctions, e.g. Si/Ge heterojunctions

Method of manufacturing semiconductor device

Life of this patent

Method of manufacturing semiconductor device

Life of this patent

Abstract

Claims20