Instruction sequence buffer to store branches having reliably predictable instruction sequences
AssigneeIntel Corporation
InventorMohammad ABDALLAH
Life of this patent
Estimating the term…
Abstract
A method for outputting reliably predictable instruction sequences. The method includes tracking repetitive hits to determine a set of frequently hit instruction sequences for a microprocessor, and out of that set, identifying a branch instruction having a series of subsequent frequently executed branch instructions that form a reliably predictable instruction sequence. The reliably predictable instruction sequence is stored into a buffer. On a subsequent hit to the branch instruction, the reliably predictable instruction sequence is output from the buffer.
Claims22
-19. (canceled)
A method for outputting reliably predictable instruction sequences, comprising:
- tracking fetches of instruction sequences from memory;
- determining instruction sequences that exceed a threshold frequency of fetches to be a reliably predictable instruction sequence;
- identifying a branch instruction preceding the instruction sequences that exceed the threshold;
- storing the reliably predictable instruction sequence into a buffer;
- and
- outputting the reliably predictable instruction sequence from the buffer into the pipeline of the processor, in response to a subsequent access of the branch instruction.
A processor pipeline for outputting reliably predictable instruction sequences, the processor pipeline comprising:
- a buffer to store reliably predictable instruction sequences;
- an instruction fetch that accesses a plurality of instructions from memory, the fetch means configured to track fetches of instruction sequences from memory, determine instruction sequences that exceed a threshold frequency of fetches to be a reliably predictable instruction sequence, identify a branch instruction preceding the instruction sequences that exceed the threshold, store the reliably predictable instruction sequence into the buffer, and output the reliably predictable instruction sequence from the buffer into the pipeline of the processor, in response to a subsequent access of the branch instruction.
A computing system comprising:
- a memory to store instructions;
- and
- a processor, wherein the processor includes a processor pipeline configured to output reliably predictable instruction sequences, the processor pipeline including a buffer to store reliably predictable instruction sequences, an instruction fetch that accesses a plurality of instructions from memory, the instruction fetch configured to track fetches of instruction sequences from memory, determine instruction sequences that exceed a threshold frequency of fetches to be a reliably predictable instruction sequence, identify a branch instruction preceding the instruction sequences that exceed the threshold, store the reliably predictable instruction sequence into a buffer, and output the reliably predictable instruction sequence from the buffer into the pipeline of the processor, in response to a subsequent access of the branch instruction.
Dependencies are inferred from the claim text.