Performing Rounding Operations Responsive To An Instruction
AssigneeIntel Corporation
InventorsRonen Zohar, Shane Story
Life of this patent
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Abstract
In one embodiment, the present invention includes a method for receiving a rounding instruction and an immediate value in a processor, determining if a rounding mode override indicator of the immediate value is active, and if so executing a rounding operation on a source operand in a floating point unit of the processor responsive to the rounding instruction and according to a rounding mode set forth in the immediate operand. Other embodiments are described and claimed.
Claims19
A processor comprising:
- a source vector register to store a plurality of packed double-precision floating-point values associated with a source operand of a round instruction;
- and
- an execution circuit to round the plurality of packed double-precision floating-point values to generate a plurality of rounded integral packed double-precision floating point values to be stored in a destination vector register, the execution circuit to round in accordance with an immediate having a plurality of bits including a first set of one or more bits to specify the rounding mode to be used by the execution circuit and a second set of one or more bits to indicate whether a precision exception is to be suppressed.
A method comprising:
- storing a plurality of packed double-precision floating-point values associated with a source operand of a round instruction in a source vector register;
- and
- rounding the plurality of packed double-precision floating-point values to generate a plurality of rounded integral packed double-precision floating point values to be stored in a destination vector register, wherein rounding is perform in accordance with an immediate having a plurality of bits including a first set of one or more bits to specify the rounding mode and a second set of one or more bits to indicate whether a precision exception is to be suppressed.
A machine-readable medium having program code stored thereon which, when executed by a machine, causes the machine to perform the operations of:
- storing a plurality of packed double-precision floating-point values associated with a source operand of a round instruction in a source vector register;
- and
- rounding the plurality of packed double-precision floating-point values to generate a plurality of rounded integral packed double-precision floating point values to be stored in a destination vector register, wherein rounding is perform in accordance with an immediate having a plurality of bits including a first set of one or more bits to specify the rounding mode and a second set of one or more bits to indicate whether a precision exception is to be suppressed.
Dependencies are inferred from the claim text.