Integrated system and method for testing system timing margin

A processing device comprising:

• a controller;
• a first clock circuit, the first clock circuit generating a first clock signal, the first clock signal being a main clock signal provided for operation of the processing device;
• and
• a built-in-test circuit for testing a system timing margin of the processing device, the built-in-test circuit comprising:
• a second clock circuit integrated with the processing device that generates a second clock signal that is asynchronous relative to the first clock signal;
• and
• a logic circuit integrated with the processing device that processes the first and second clock signals and outputs a third clock signal that is used to determine system timing margin of the processing device.

A method of testing a system timing margin of a processing device under-test, the method comprising:

• generating, internal to the processing device, a second clock signal that is asynchronous relative to a first clock signal, the first clock signal being a main clock signal provided for operation of the processing device;
• processing, internal to the processing device, the first clock signal and the second clock signal;
• outputting a third clock signal based on the processing of the first and second clock signals;
• and
• determining system timing margin of the processing device using the third clock signal.