Back to results
US 2017/0322520 A1Published application
Time register
AssigneeHuawei Technologies Co., Ltd.
InventorsYing WU, Robert Bogdan STASZEWSKI, Yihong MAO
Life of this patent
Estimating the term…
Abstract
A time register includes: a pair of inputs coupled to a pair of input clocks; a pair of tri-state inverters for producing a pair of level signals; and a pair of outputs coupled to the level signals for producing a pair of output clocks, wherein the tri-state inverters are responsive to a pair of state signals and the pair of input clocks for holding or discharging the level signals.
Claims15
A time register comprising:
- a pair of inputs coupled to a pair of input clocks;
- a pair of tri-state inverters for producing a pair of level signals;
- and
- a pair of outputs coupled to the level signals for producing a pair of output clocks,
- wherein the tri-state inverters are responsive to a pair of state signals and the pair of input clocks for holding or discharging the level signals.
2 more elements
A time register comprising a first circuit and a second circuit), each of the circuits comprising:
- a tri-state inverter coupled between a capacitive loaded first node and an output node, the tri-state inverter comprising:
- a PMOS transistor coupled between a battery voltage and the first node);
- and
- a first NMOS transistor and a second NMOS transistor coupled in series between the first node and a reference voltage,
- wherein a control terminal of the PMOS transistor and a control terminal of the first NMOS transistor are driven by an input signal and a control terminal of the second NMOS transistor is driven by a state signal, and
- wherein the tri-state inverter is configured to propagate a time difference between the input signal and the state signal to a voltage level at the first node.
3 more elements
Dependencies are inferred from the claim text.