Overlay architecture for programming fpgas
AssigneeUniversity of Florida Research Foundation, Inc.
InventorsJames R. Coole, Gregory M. Stitt
Life of this patent
Estimating the term…
Abstract
An overlay architecture and an associated method that uses datapath merging to provide minimal-overhead support for multiple source netlists, and optionally provides an adjustable amount of flexibility through a secondary interconnect network is disclosed.
Claims19
A method of operating a computing device to generate, from a specification of functionality, a bitstream to program an FPGA, the FPGA comprising a plurality of configurable logic elements and a plurality of configurable interconnection elements among the logic elements, and the bitstream specifying a configuration of at least a portion of the configurable logic elements and a portion of the configurable interconnection elements, the method comprising:
- selecting an overlay from a library of a plurality of overlays, wherein each overlay defines a plurality of functional units and a plurality of configurable interconnects among the plurality of functional units, and programming information specifying, at least in part, a configuration of the FPGA to implement the plurality of functional units;
- generating, based on the specification of functionality, a defined configuration of the configurable interconnects that interconnects functional units of the plurality of functional units in accordance with the specification of functionality;
- generating, based on at least the defined configuration and the programming information of the selected overlay, a bitstream to configure the FPGA to implement functionality according to the specification of functionality.
At least one non-transitory computer-readable medium encoded with:
- an overlay defining a plurality of functional units and a plurality of configurable interconnects among the plurality of functional units, and programming information specifying, at least in part, a configuration of an FPGA to implement the plurality of functional units and a configuration of the configurable interconnects;
- computer executable instructions that, when executed, control at least one processor to perform a method of operating a computing device to generate, from a specification of functionality, a bitstream to program the FPGA, the FPGA comprising a plurality of configurable logic elements and a plurality of configurable interconnection elements among the logic elements, and the bitstream specifying a configuration of at least a portion of the configurable logic elements and a portion of the configurable interconnection elements, the method comprising:
- generating, based on the specification of functionality, a defined configuration of the configurable interconnects that interconnects functional units of the plurality of functional units in accordance with the specification of functionality;
- generating, based on at least the defined configuration and the programming information of the selected overlay, a bitstream to configure the FPGA to implement functionality according to the specification of functionality.
A method of operating a computing device to generate, from a specification of functionality, a bitstream to program an FPGA, the FPGA comprising a plurality of configurable logic elements and a plurality of configurable interconnection elements among the logic elements, and the bitstream specifying a configuration of at least a portion of the configurable logic elements and a portion of the configurable interconnection elements. The method comprising:
- at a first time, generating a first portion of the bitstream representative of an overlay defining a plurality of functional units and a plurality of configurable interconnects among the plurality of functional units, the first portion of the bitstream comprising programming information for at least a portion of the configurable logic elements to implement the plurality of functional units;
- at a second time:
- generating a configuration for the plurality of configurable interconnects of the overlay based on the specification of functionality;
- and
- generating a second portion of the bitstream representative of the configuration for the plurality of configurable interconnects of the overlay, the second portion of the bitstream comprising programming information for at least a portion of the configurable interconnection elements to implement the plurality of configurable interconnects of the overlay;
- and
- programming the FPGA with the bitstream.
Dependencies are inferred from the claim text.