Write delivery for memory subsystem with narrow bandwidth repeater channel

A memory system, comprising:

• a memory controller circuit to control access to memory;
• a first memory module to couple to the memory controller circuit via a primary segment of a memory channel, the first memory module including multiple dynamic random access memory (DRAM) devices and a repeater, and the primary segment of the memory channel with a bandwidth for commands from the memory controller circuit;
• and
• a second memory module to couple to the memory controller circuit through the repeater via a secondary segment of the memory channel, the second memory module including multiple DRAM devices, and the secondary segment of the memory channel with a portion of the bandwidth for commands from the memory controller circuit, the portion less than the bandwidth;
• wherein the repeater is to provide access to up to the portion of the bandwidth for commands to the second memory module, and to provide access to at least an amount equal to the bandwidth less the portion for commands to the first memory module.