US 2017/0289481 A1Published application

Imaging device

AssigneePanasonic Intellectual Property Management Co., Ltd.

InventorsHIDENARI KANEHARA, YASUO MIYAKE, SANSHIRO SHISHIDO

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Abstract

An imaging device includes: first and second pixel cells each including a photoelectric converter and a transistor electrically connected to the photoelectric converter, the transistor having a control terminal; a first buffer circuit having a first input terminal and a first output terminal, the first buffer circuit receiving a signal for controlling the transistor of the first pixel cell; a second buffer circuit having a second input terminal and a second output terminal, the second buffer circuit receiving a signal for controlling the transistor of the second pixel cell; a first control signal line connecting the first output terminal to the control terminal of the first pixel cell; and a second control signal line connecting the second output terminal to the control terminal of the second pixel cell. The first control signal line and the second control signal line are connected to each other.

Claims17

Dependent claims

An imaging device, comprising:

a first pixel cell including a first photoelectric converter and a first transistor electrically connected to the first photoelectric converter, the first transistor having a first control terminal;
a second pixel cell including a second photoelectric converter and a second transistor electrically connected to the second photoelectric converter, the second transistor having a second control terminal;
a first buffer circuit having a first input terminal and a first output terminal, the first buffer circuit receiving a signal for controlling the first transistor through the first input terminal;
a second buffer circuit having a second input terminal and a second output terminal, the second buffer circuit receiving a signal for controlling the second transistor through the second input terminal;
a first control signal line connecting the first output terminal to the first control terminal;
and
a second control signal line connecting the second output terminal to the second control terminal, wherein
the first control signal line and the second control signal line are connected to each other.

5 more elements

Dependencies are inferred from the claim text.

Facts

Application: 15/458,933Filed 14 Mar 2017
Priority: JP 2016-06792430 Mar 2016
Published: 5 Oct 2017
Term ends: Not estimatedThe source records don’t support an estimate.

Classification10 codes

H04N 25/77
Addressed sensors, e.g. MOS or CMOS sensors: pixel circuitry, e.g. memories, A/D converters, pixel amplifiers, shared circuits or shared components
H04N 25/705
SSIS architectures incorporating pixels for producing signals other than image signals: pixels for depth measurement, e.g. RGBZ
H04N 25/766
Addressed sensors, e.g. MOS or CMOS sensors: comprising control or output lines used for a plurality of functions, e.g. for pixel output, driving,…
H04N 25/779
Addressed sensors, e.g. MOS or CMOS sensors: circuitry for scanning or addressing the pixel array

Family

US 10,178,335 B2Related patent
US 2017/0289481 A1This patent

From the US filing history. Foreign family members aren’t listed.

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