Correlated double sampling (cds) circuit for decreasing settling time and image sensor including the same

A correlated double sampling (CDS) circuit comprising:

• a comparator, the comparator including,
• a first input terminal,
• a second input terminal,
• at least one output terminal, and
• a plurality of first transistors operably coupled between the at least one output terminal and the first and second input terminals,
• a first circuit including at least one second transistor, the at least one second transistor operably coupled to the at least one output terminal and one of the first input terminal and the second input terminal, the at least one second transistor having at least one of (i) a different number of layers than the first transistors, and (ii) a different dimension than the first transistors.

An image sensor comprising:

• a pixel array having a plurality of pixels, at least one of the plurality of pixels configured to generate a pixel signal;
• and
• a correlated double sampling (CDS) circuit configured to receive the pixel signal, the CDS circuit further including,
• a comparator, the comparator including,
• a first input terminal configured to receive at least a portion of the pixel signal,
• a second input terminal,
• at least one output terminal configured to output an output signal based on the pixel signal, and
• a plurality of first transistors operably coupled between the at least one output terminal and the first and second input terminals,
• a first circuit including at least one second transistor, the at/least one second transistor operably coupled to the at least one output terminal and one of the first input terminal and the second input terminal, the at least one second transistor having at least one of (i) a different number of layers than the first transistors, and (ii) a different dimension than the first transistors.