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US 2017/0288915 A1Published application
Systems and Methods for Mitigating Over-Equalization in a Short Channel
AssigneeAvago Technologies General IP (Singapore) Pte. Ltd.
InventorsNayak Ratnakar Aravind, Mohammad Mobin, Thomas Gibbons
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Abstract
Embodiments are related to systems and methods for data processing, and more particularly to systems and methods for clock recovery in a data receiver.
Claims20
A data transfer system, the system comprising:
- a receiver circuit operable to recover a data input from a data transfer set to yield a data output, wherein the receiver circuit includes:
- a gain and equalization adaptation circuit operable to adaptively calculate an equalizer coefficient and a gain control;
- and
- an over-equalization mitigation constraint circuit operable to increment the gain control to yield an updated gain control based at least in part on the equalizer coefficient
- wherein the over-equalization mitigation constraint circuit is operable to increment the gain control to yield an updated gain control when the equalization coefficient is greater than a minimum allowable value and the gain control is below a maximum allowable value.
2 more elements
A method for data transmission, the method comprising:
- receiving a data transfer set by a receiver circuit;
- using a variable gain amplifier circuit to amplify a first data input derived from the data transfer set to yield an amplified output, wherein amplification by the variable gain amplifier circuit is governed at least in part based upon a gain control;
- using an equalizer circuit to equalize a second data input derived from the first data input to yield an equalized output, wherein equalization by the equalizer circuit is governed at least in part based upon an equalizer coefficient;
- and
- adaptively modifying at least one of the equalizer coefficient and the gain control based at least in part on an error value,
- wherein adaptively modifying the at least one of the equalizer coefficient and the gain control based at least in part on the error value includes incrementing the gain control when the equalizer coefficient is greater than a minimum allowable value and the gain control is less than a maximum allowable value.
3 more elements
A storage device, the storage device comprising:
- a receiver circuit operable to recover a data input from a data transfer set to yield a data output, wherein the receiver circuit includes:
- a gain and equalization adaptation circuit operable to adaptively calculate an equalizer coefficient and a gain control;
- an over-equalization mitigation constraint circuit operable to increment the gain control to yield an updated gain control based at least in part on the equalizer coefficient;
- and
- a serial data recovery circuit including an equalizer circuit operable to equalize an input set derived from the data transfer set to yield the data input, wherein operation of the equalizer circuit is governed at least in part based upon the equalizer coefficient;
- and
- a transmission circuit operable to prepare the data input for transmission to the receiver circuit,
- wherein the over-equalization mitigation constraint circuit is operable to increment the gain control to yield the updated gain control when the equalization coefficient is greater than the minimum allowable value and the gain control less than a maximum allowable value.
5 more elements
Dependencies are inferred from the claim text.