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AssigneeIntel Corporation
InventorsRaghavan Kumar, Sanu K. Mathew, Sudhir K. Satpathy, Vikram B. Suresh
Estimating the term…
A processing system includes a processing core and a hardware accelerator communicatively coupled to the processing core. The hardware accelerator includes a random number generator to generate a byte order indicator. The hardware accelerator also includes a first switching module communicatively coupled to the random value indicator generator. The switching module receives an byte sequence in an encryption round of the cryptographic operation and feeds a portion of the input byte sequence to one of a first substitute box (S-box) module or a second S-box module in view of a byte order indicator value generated by the random number generator.
A processing system comprising:
A system-on-a chip (SoC) comprising:
A method comprising:
A non-transitory machine-readable storage medium including instructions that, when accessed by a processing device, cause the processing device to perform operations comprising:
Dependencies are inferred from the claim text.