Ldpc shuffle decoder with initialization circuit comprising ordered set memory

A low-density parity check (LDPC) decoding apparatus for performing shuffle decoding, comprising:

• an input wrapper, for receiving input data comprising a plurality of codewords and error-correction information, and padding the input data;
• an LDPC decoder, coupled to the input wrapper, for receiving the padded input data, performing a plurality of iterations of LDPC decoding upon the padded input data according to the error-correction information to generate channel values, and outputting a hard decision channel value in a final iteration;
• and
• an initialization circuit, coupled to the LDPC decoder, for receiving the input data in a first iteration of the plurality of iterations, storing the input data into an ordered set data, and immediately sending the ordered set data to the LDPC decoder, so that the error-correction information can be used to perform LDPC decoding upon the padded input data in the first iteration.