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US 2017/0288683 A1Published application
Coarse delay lock estimation for digital dll circuits
AssigneeIntel Corporation
InventorsFangxing Wei, Khushal Chandan, Dan Shi, Michael Allen
Life of this patent
Estimating the term…
Abstract
Digital delay locked loop circuits, devices systems, and associated methods are provided and described. Such devices, systems, and methods utilize an open loop measurement for establishing a coarse delay lock.
Claims26
An electronic device, comprising:
- delay-locked loop (DLL) circuitry configured to:
- receive a reference clock signal from a reference clock source;
- compare a number of positive clock edges of the reference clock signal to a number of negative clock edges of the reference clock signal within an initial delay test window;
- increase the duration of the initial delay test window by a delay increment if the number of positive clock edges does not equal the number of negative clock edges;
- repeat receipt of the reference clock signal, comparison of the number of positive to negative clock edges, and increase the duration of the delay test window until the number of positive and negative clock edges in the delay test window are equal;
- and
- coarse lock a strobe signal to the reference clock signal with a coarse delay equal to a total duration increase of the delay test window.
4 more elements
A delay locked-loop (DLL) circuit, comprising:
- a closed loop fine delay tracking circuit;
- a variable delay circuit;
- an open loop coarse delay matching circuit to determine a coarse delay code by testing a current coarse delay code, further comprising:
- a pair of shift registers each comprised of a plurality of flip flops configured such that one of the pair of shift registers is responsive to positive clock edges and the other is responsive to negative clock edges;
- a reference clock input to each flip flop;
- a compare circuit coupled between the pair of shift registers;
- a state machine coupled to a first flip flop of each of the pair of shift registers, and configured to introduce a high value into each first flip flop;
- and
- a reference clock delay loop coupled from the reference clock input through the variable delay circuit to each flip flop, and configured to de-activate the pluralities of flip flops.
6 more elements
An open loop coarse delay matching circuit, comprising:
- a variable delay circuit;
- a pair of shift registers each comprised of a plurality of flip flops configured such that one of the pair of shift registers is responsive to positive clock edges and the other is responsive to negative clock edges;
- a reference clock input to each flip flop;
- a compare circuit coupled between the pair of shift registers;
- a state machine coupled to a first flip flop of each of the pair of shift registers, and configured to introduce a high value into each first flip flop;
- and
- a reference clock delay loop coupled from the reference clock input through the variable delay circuit to each flip flop, and configured to de-activate the pluralities of flip flops.
4 more elements
Dependencies are inferred from the claim text.