Device and method for multiple reference system timer

A method for timing control, the method comprising the steps of:

• generating at least one high frequency reference clock;
• generating a low frequency reference clock;
• and
• generating a system timer by processing the at least one high frequency reference clock and the low frequency reference clock,
• wherein the system timer is used for timing synchronization in a wireless communication terminal.

An apparatus for timing control in a wireless communications terminal, comprising:

• a plurality of high frequency reference clocks;
• a scaled high frequency reference clock;
• a low frequency reference clock;
• a time delayed low frequency reference clock;
• timing block logic for selecting one of the plurality of high frequency reference clocks;
• a prescaler circuit for dividing the selected one of the plurality of high frequency reference clocks to generate the scaled high frequency reference clock;
• a temperature measurement unit for measuring the temperature of the low frequency reference clock;
• a temperature compensation look up table;
• a processor for correcting frequency error in the low frequency reference clock using temperature measurement data from the temperature measurement unit and frequency error data from the temperature compensation look up table;
• a finite state machine including a first input connected to the prescaler circuit, a second input connected to the time delayed low frequency reference clock, a third input connected to a prescaled clock detect circuit, a first output connected to a first multiplexer select control, a second output connected to a second multiplexer select control, and a third output connected to a third multiplexer input line;
• and
• a circuit for providing a system timer to functional blocks of the wireless communications terminal including an accumulator,
• wherein the accumulator is clocked by the third multiplexer input line or the scaled high frequency reference clock as determined by the second multiplexer select control, a divide circuit for dividing the accumulator value by 2, and a register accessible by the functional blocks for providing the system timer.