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US 2017/0288677 A1Published application
Clock signal stop detection circuit
AssigneeRenesas Electronics Corporation
InventorSeima UEZATO
Life of this patent
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Abstract
A semiconductor device detects an edge of input data input into a data retention circuit to which a clock signal is supplied, resets a first count value obtained by counting an edge detection frequency with a clock signal, resets a second count value obtained by counting the edge detection frequency with an inverted clock signal, and thereby detects an abnormality of the clock signal in accordance with a situation that either of the first count value and the second count value has reached a value indicative of an overflow state.
Claims6
A semiconductor device, comprising:
- a PWM circuit that receives a clock signal and a PWM control signal, and generates a PWM signal;
- a first counter that counts an edge number of the PWM signal;
- a second counter that counts the edge number of the PWM signal;
- and
- a clock signal stop detection circuit that detects an abnormality of the clock signal when one of the first counter and the second counter reaches a predetermined value.
2 more elements
Dependencies are inferred from the claim text.