Pipelined interconnect circuitry with double data rate interconnections

Abstract

An integrated circuit may have pipelined interconnects that are configurable to operate in registered single data rate mode, registered double data rate mode, or in combinational mode. The pipelined interconnect may include routing multiplexers for selecting incoming signals, circuitry for serialization and de-serialization, and memory elements that are configurable to store one or two signals per clock period. Operating the pipeline interconnects in double data rate mode may provide a trade-off between reducing the number of physical wires that are required to implement a design at a constant bandwidth or increasing the bandwidth while keeping the number of physical wires constant.

Dependencies are inferred from the claim text.