Semiconductor Device, Electronic Component, and Electronic Device

A semiconductor device comprising:

• a context controller;
• a clock generation circuit;
• a programmable circuit;
• and
• a switch circuit,
• wherein the programmable circuit includes a programmable logic element,
• wherein the context controller includes a detection circuit, a signal generation circuit, and a determination circuit,
• wherein the detection circuit is configured to detect context switch,
• wherein the signal generation circuit is configured to generate a context signal in accordance with the context switch,
• wherein the determination circuit is configured to generate a switch signal in accordance with the context switch,
• wherein the clock generation circuit is configured to generate a second clock signal,
• wherein a frequency of the second clock signal is lower than a frequency of a first clock signal, and
• wherein the switch circuit is configured to supply the first clock signal or the second clock signal to the programmable logic element in response to the switch signal.

A semiconductor device comprising:

• a context controller;
• a clock generation circuit;
• a programmable circuit;
• and
• a switch circuit,
• wherein the programmable circuit includes a programmable logic element,
• wherein the programmable logic element includes a flip-flop and a backup circuit capable of retaining data retained in the flip-flop,
• wherein the context controller includes a detection circuit, a signal generation circuit, and a determination circuit,
• wherein the detection circuit is configured to detect context switch,
• wherein the signal generation circuit is configured to generate a context signal in accordance with the context switch,
• wherein the determination circuit is configured to generate a switch signal in accordance with the context switch,
• wherein the clock generation circuit is configured to generate a second clock signal and a third clock signal,
• wherein a frequency of the second clock signal and a frequency of the third clock signal are lower than a frequency of a first clock signal,
• wherein the clock generation circuit outputs the second clock signal in a period during which data is input from the flip-flop to the backup circuit and outputs the third clock signal in a period during which the data is input from the backup circuit to the flip-flop, and
• wherein the switch circuit is configured to supply the first clock signal, the second clock signal, or the third clock signal to the programmable logic element in response to the switch signal.