US 2017/0288664 A1Published application

Multi-orientation integrated cell, in particular input/output cell of an integrated circuit

AssigneesSTMicroelectronics S.r.l., STMicroelectronics (Crolles 2) SAS

InventorsAlexandre Dray, Emmanuel Josse

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Abstract

An integrated circuit includes at least one integrated cell disposed at a location of the integrated circuit. The at least one integrated cell may have two integrated devices coupled to at least one site of the integrated cell and a multiplexer, and the two integrated devices respectively oriented in two different directions of orientation. A first integrated device of the two integrated devices that is oriented in one of the two directions of orientation is usable. The integrated circuit may include a controller configured to detect the direction of orientation which, having regard to the disposition of the integrated cell at the location, may allow the first integrated device to be usable, and to control the multiplexer to couple the first integrated device electrically to the at least one site.

Claims19

Dependent claims

An integrated circuit, comprising:

a multiplexer coupled to a site of an integrated cell disposed at a location of an integrated circuit;
a first thin gate oxide transistor configured to exhibit normal operation in a first direction of orientation and degraded operation in a second direction of orientation, the first thin gate oxide transistor having a terminal coupled to a first input terminal of the multiplexer;
a second thin gate oxide transistor configured to exhibit normal operation in the second direction of orientation and degraded operation in the first direction of orientation, the second thin gate oxide transistor having a terminal coupled to a second input terminal of the multiplexer;
and
a controller configured to detect a usability of the first thin gate oxide transistor and the second thin gate oxide transistor based on an electrical characteristic indicative of the first direction of orientation or the second direction of orientation, the controller being further configured to control the multiplexer to couple the terminal of the first thin gate oxide transistor or the terminal of the second thin gate oxide transistor to the site.

2 more elements

A method of operating an integrated circuit, the method comprising:

detecting, by a controller, a usability of a first integrated device and a second integrated device based on an electrical characteristic indicative of a first direction of orientation or a second direction of orientation, the first integrated device exhibiting normal operation in the first direction of orientation and degraded operation in the second direction of orientation, the second integrated device exhibiting degraded operation in the first direction of orientation and normal operation in the second direction of orientation;
sending, by the controller, a control signal to a multiplexer based on the usability of the first integrated device and the second integrated device detected by the controller;
and
coupling, by the multiplexer and based on the control signal, a terminal of the first integrated device or a terminal of the second integrated device to a site of an integrated cell disposed at a location of an integrated circuit. ii. The method of claim 10, wherein the first direction of orientation is orthogonal to the second direction of orientation.

1 more element

An integrated circuit, comprising:

a first integrated device being operable in a first direction of orientation and exhibiting degraded operation in a second direction of orientation compared to the first direction of orientation;
a second integrated device being operable in the second direction of orientation and exhibiting degraded operation in the first direction of orientation compared to the second direction of orientation;
a multiplexer having input terminals coupled to the first integrated device and the second integrated device, the multiplexer being configured to couple, based on a control signal, the first integrated device or the second integrated device to a site of an integrated cell disposed at a location of the integrated circuit;
and
a controller configured to determine an operability of the first integrated device and the second integrated device and generate the control signal based on the operability of the first integrated device and the second integrated device.

2 more elements

Dependencies are inferred from the claim text.

Facts

Application: 15/630,469Filed 22 Jun 2017
Priority: FR 146087712 Nov 2014
Published: 5 Oct 2017
Term ends: Not estimatedThe source records don’t support an estimate.

Classification9 codes

H03K 17/687
By the use, as active elements, of semiconductor devices: the devices being field-effect transistors
G01R 31/2884
Testing of integrated circuits [IC]: using dedicated test connectors, test elements or test circuits on the IC under test
H10D 89/10
Aspects of integrated devices not covered by groups H10D84/00 - H10D88/00: integrated device layouts
H10P 74/232
Characterised by multiple measurements, corrections, marking or sorting processes: comprising connection or disconnection of parts of a device in…

Family

Application14/865,618Continuation · filed 25 Sep 2015
Application15/630,469Continuation
US 2016/0134282 A1Published application
US 9,735,772 B2Related patent
US 2017/0288664 A1This patent

From the US filing history. Foreign family members aren’t listed.

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