Resistor array, output buffer, and manufacturing method for semiconductor device
AssigneeLapis Semiconductor Co., Ltd.
InventorSeiichiro SASAKI
Life of this patent
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Abstract
A resistor array made of a semiconductor includes a plurality of resistor groups and a common line that electrically connects the M-th resistors of the plurality of resistor groups. Each resistor group includes first to M-th resistors connected in series, M being an integer of 2 or greater, and at least one short-circuit line, each short-circuiting at least one, but not all, of the M resistors.
Claims11
A resistor array made of a semiconductor, comprising:
- a plurality of resistor groups, each including
- first to M-th resistors connected in series, M being an integer of 2 or greater, and
- at least one short-circuit line, each short-circuiting at least one, but not all, of the M resistors;
- and
- a common line that electrically connects the M-th resistors of the plurality of resistor groups.
An output buffer for receiving an input signal and outputting an output signal through an external terminal, comprising:
- an output resistor circuit including
- a plurality of resistor groups, each including
- first to M-th resistors connected in series, M being an integer of 2 or greater, and
- at least one short-circuit line, each short-circuiting at least one, but not all, of the M resistors;
- and
- a common line that electrically connects the M-th resistors of the plurality of resistor groups;
- and
- a driver circuit including a plurality of drivers respectively corresponding to the plurality of resistor groups, each driver supplying an amplified signal, obtained by amplifying the input signal, to the corresponding one of the plurality of resistor groups.
An output buffer for receiving an input signal and outputting an output signal through an external terminal, comprising:
- an output resistor circuit including first to n-th resistor circuits, and a common line that electrically connects one end of each of the first to n-th resistor circuits to the external terminal, n being an integer of 2 or greater;
- first to n-th three-state drivers respectively supplying first to n-th amplified signals, which are obtained by amplifying the input signal, to the first to n-th resistor circuits, each at the other end thereof;
- and
- an output impedance adjusting circuit configured to supply first to n-th enable-disable signals to the first to n-th three-state drivers, respectively, to thereby enable or disable the first to n-th three-state drivers.
Dependencies are inferred from the claim text.