Device for correcting multi-phase clock signal

A device for correcting a multi-phase clock signal, the device comprising:

• a first duty ratio adjusting circuit configured to adjust a duty ratio of a first clock signal having a first phase;
• a variable delay line configured to variably delay a second clock signal having a second phase;
• a second duty ratio adjusting circuit configured to adjust a duty ratio of an output of the variable delay line;
• a first differential clock generating circuit configured to generate a first differential signal from an output of the first duty ratio adjusting circuit;
• a second differential clock generating circuit configured to generate a second differential signal from an output of the second duty ratio adjusting circuit;
• an edge combining circuit configured to combine edges of signals output from the first differential clock generating circuit and the second differential clock generating circuit;
• a duty ratio detecting circuit configured to detect a duty ratio of either an output from the first duty ratio adjusting circuit or an output from the first differential clock generating circuit when in a duty ratio correction mode and configured to detect a duty ratio of an output from the edge combining circuit when in a phase correction mode;
• a first control circuit configured to control the first duty ratio adjusting circuit and the second duty ratio adjusting circuit in accordance with an output of the duty ratio detecting circuit when the duty ratio detecting circuit is in the duty ratio correction mode;
• and
• a second control circuit configured to control the variable delay line in accordance with an output of the duty ratio detecting circuit when the duty ratio detecting circuit is in the phase correction mode.