Semiconductor device

A semiconductor device comprising:

• a gate line connected to a gate terminal of a power device including an first terminal, a second terminal, and the gate terminal;
• a plurality of first constant-current circuits connected between the gate line and a power supply line;
• a plurality of second constant-current circuits connected between the gate line and a ground line;
• a constant-current circuit selecting circuit configured to select a constant-current circuit to be activated from among the plurality of first constant-current circuits and the plurality of second constant-current circuits and output an activation instruction signal to the selected constant-current circuit;
• a first comparator configured to change a level of a first voltage detection signal from a first logical level to a second logical level when a voltage at the gate terminal becomes higher than a first threshold voltage;
• a second comparator configured to change a level of a second voltage detection signal from the first logical level to the second logical level when the voltage at the gate terminal becomes higher than a second threshold voltage;
• and
• a gate mode setting circuit configured to control an on/off-state of the constant-current circuit selected by the constant-current circuit selecting circuit based on a gate control signal for controlling an on/off-state of the power device, the activation instruction signal, the first voltage detection signal, and the second voltage detection signal, wherein
• the gate mode setting circuit controls the on/off-state of the constant-current circuit selected by the constant-current circuit selecting circuit in a period in which the first and second voltage detection signals have different logical levels, and
• the gate mode setting circuit increases the number of constant-current circuits that are controlled to an on-state compared to the number of constant-current circuits controlled to an on-state in the period in which the first and second voltage detection signals have different logical levels in a period in which the first and second voltage detection signals have the same logical level.