Electrostatic discharge (esd) isolated input/output (i/o) circuits

An electrostatic discharge (ESD) protected serializer/deserializer (SERDES) differential receiver circuit, comprising:

• an input/output (I/O) receiver circuit including a first transistor receiver and a second transistor receiver, each have having a gate coupled to a differential input pad, and a drain coupled to an internal differential output;
• a first load transistor selectively coupled between a power supply terminal and the first transistor receiver, and a second load transistor selectively coupled between the power supply terminal and the second transistor receiver of the I/O receiver circuit;
• a common mode transistor selectively coupled between a ground terminal, the first transistor receiver and the second transistor receiver of the I/O receiver circuit;
• and
• an ESD detector circuit configured to selectively disengage the power supply terminal from the first transistor receiver and the second transistor receiver of the I/O receiver circuit, and configured to selectively disengage the ground terminal from the first transistor receiver and the second transistor receiver of the I/O receiver circuit.

A method of protecting a serializer/deserializer (SERDES) differential input/output (I/O) circuit, comprising:

• detecting an electrostatic discharge event;
• selectively disengaging a power supply terminal from a pair of I/O transistors of the SERDES differential I/O circuit in response to the detected electrostatic discharge event;
• and
• selectively disengaging a ground terminal from the pair of I/O transistors of the SERDES differential I/O circuit in response to the detected electrostatic discharge event.

An electrostatic discharge (ESD) protected serializer/deserializer (SERDES) differential driver circuit, comprising:

• an input/output (I/O) driver circuit including a first transistor driver and a second transistor driver, each having a drain coupled to a differential output pad;
• a pre-driver circuit including a first pre-driver inverter coupled to a gate of the first transistor driver, and a second pre-driver inverter coupled to a gate of the second transistor driver, in which the pre-driver circuit is selectively coupled between a power supply terminal and a ground terminal;
• a switch transistor selectively coupled between the power supply terminal, the first transistor driver, and the second transistor driver of the I/O driver circuit;
• a common mode transistor selectively coupled between the ground terminal, the first transistor driver and the second transistor driver of the I/O driver circuit;
• and
• means for selectively disengaging the power supply terminal from the first transistor driver and the second transistor driver of the I/O driver circuit, and means for selectively disengaging the ground terminal from the first transistor driver and the second transistor driver of the I/O driver circuit.