Fail-Safe For Shared Pin
AssigneeTexas Instruments Incorporated
InventorsSumit Dubey, Nitin Agarwal
Life of this patent
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Abstract
An integrated circuit (IC) provides an improved fail-safe signal to a circuit sharing a fail-safe pin at which the voltage can be greater than the voltage of an upper rail. The IC includes a first circuit segment that receives a first fail-safe signal and a first power-down signal and provides an intermediate signal, wherein the first fail-safe signal indicates when the voltage at the fail-safe pin is greater than the upper rail and the first power-down signal indicates when the module is powered down, and a second circuit segment connected to receive the intermediate signal and to provide the improved fail-safe signal to the module.
Claims11
An integrated circuit (IC) for providing an improved fail-safe signal to a circuit sharing a fail-safe pin at which a voltage can be greater than a voltage of an upper rail, the IC comprising:
- a first circuit segment that receives a first fail-safe signal and a first power-down signal and provides an intermediate signal, wherein the first fail-safe signal indicates when the voltage at the fail-safe pin is greater than the upper rail and the first power-down signal indicates when the module is powered down;
- and
- a second circuit segment connected to receive the intermediate signal and to provide the improved fail-safe signal to the module.
An integrated circuit (IC) chip comprising:
- a plurality of circuit blocks that share a common pin, wherein a voltage at the common pin can be greater than a voltage of an upper rail;
- a first circuit block of the plurality of circuit blocks, the first circuit block comprising a PMOS transistor coupled in series between the common pin and the upper rail;
- and
- a fail-safe circuit that receives the voltage at the common pin and a power-down signal for the first circuit block and provides a first fail-safe signal that turns off the PMOS transistor whenever the voltage at the common pin is greater than the upper rail and also when the first circuit block is in power-down mode.
Dependencies are inferred from the claim text.