US 2017/0288327 A1 · HARDWARE INTERFACE WITH SPACE-EFFICIENT CELL PATTERN

Abstract

Techniques and mechanisms for providing connectivity to an integrated circuit device via a hardware interface. In an embodiment, the hardware interface includes contacts forming an array of nodes. Some or all such nodes are arranged in cells, wherein the respective node types of each cell's nodes are according to the same cell pattern. The cell pattern includes eight B nodes for the exchange of data bits, four strobe S nodes for the exchange of strobe signals, and ground (G) nodes for the providing of one or more reference potentials. The cell pattern enables formation of a lattice structure including node-contiguous G nodes each of a respective one of the multiple cells. In another embodiment, a ratio of bi-level nodes (including all S nodes and all G nodes) of the cell pattern to a total number of G nodes of the cell pattern is 12:8 or more.

Claims20

Dependent claims

A device comprising:

a hardware interface including conductive contacts arranged as an array of nodes, the array comprising a plurality of cells each having a cell pattern including:
eight data bit (B) nodes;
four strobe (S) nodes;
and
ground (G) nodes;
wherein a first column at a first side of the cell pattern includes a first node-contiguous group of three or more G nodes of the cell pattern, wherein a first row at a second side of the cell pattern includes a second node-contiguous group of three or more G nodes of the cell pattern;
wherein, for each column of the cell pattern, the column includes a G node that, of the nodes of the column, is closest, column-wise, to the first row;
and
wherein each B node of the cell pattern is row-adjacent or column-adjacent to at least one respective S node of the cell pattern.

6 more elements

A method comprising:

coupling a first device to a second device via a hardware interface including conductive contacts arranged as an array of nodes, the array comprising a plurality of cells each having a cell pattern including:
eight data bit (B) nodes;
four strobe (S) nodes;
and
ground (G) nodes;
wherein a first column at a first side of the cell pattern includes a first node-contiguous group of three or more G nodes of the cell pattern, wherein a first row at a second side of the cell pattern includes a second node-contiguous group of three or more G nodes of the cell pattern;
wherein, for each column of the cell pattern, the column includes a G node that, of the nodes of the column, is closest, column-wise, to the first row;
and
wherein each B node of the cell pattern is row-adjacent or column-adjacent to at least one respective S node of the cell pattern;
exchanging signals between the first device and the second device via the hardware interface.

7 more elements

Dependencies are inferred from the claim text.

Hardware interface with space-efficient cell pattern

Life of this patent

Hardware interface with space-efficient cell pattern

Life of this patent

Abstract

Claims20