Embedded chip packages and methods for manufacturing an embedded chip package
AssigneeInfineon Technologies AG
InventorsGottfried Beer, Walter Hartner
Life of this patent
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Abstract
A method for manufacturing an embedded chip package is provided. The method may include: forming electrically conductive lines over a substrate; placing the substrate next to a chip arrangement comprising a chip, the chip comprising one or more contact pads, wherein one or more of the electrically conductive lines are arranged proximate to a side wall of the chip; and forming one or more electrical interconnects over the chip arrangement to electrically connect at least one electrically conductive line to at least one contact pad.
Claims17
A method for manufacturing an embedded chip package, the method comprising forming a first layer of electrically conductive lines over a substrate to form a pre-formed via arrangement;
- dicing the pre-formed via arrangement in a direction perpendicular to the electrically conductive lines;
- placing the diced pre-formed via arrangement perpendicularly next to a first side of a chip arrangement comprising a chip, the chip comprising a chip bottom side and a chip top side comprising one or more contact pads, wherein one or more of the electrically conductive lines are arranged proximate to a first side wall of the chip and wherein the diced pre-formed via arrangement is turned so that the electrically conductive lines are facing the first side wall of the chip;
- and
- subsequent to the placing the diced pre-formed via arrangement next to the chip arrangement, forming one or more electrical interconnects over the chip arrangement substantially perpendicular to the electrically conductive lines and substantially parallel to a top side of the chip so as to electrically connect at least one electrically conductive line to at least one of the contact pads.
A method for manufacturing an embedded chip package, the method comprising:
- forming a first layer of electrically conductive lines over a first substrate side to form a pre-formed via arrangement, wherein each electrically conductive line is covered by electrically insulating material at least partially surrounding the electrically conductive lines;
- dicing the pre-formed via arrangement in a direction perpendicular to the electrically conductive lines;
- placing a surface of the diced pre-formed via arrangement perpendicularly next to a first side of a chip arrangement comprising a chip, the chip comprising a chip bottom side and a chip top side comprising one or more contact pads, wherein the first layer of electrically conductive lines are arranged proximate to a first side wall of the chip and wherein the diced pre-formed via arrangement is turned so that the electrically conductive lines are facing the first side wall of the chip;
- and
- subsequent to the placing the diced pre-formed via arrangement next to the chip arrangement, forming at least one electrical interconnect over the chip arrangement substantially perpendicular to the successive layers of electrically conductive lines and parallel to a top side of the chip so as to electrically connect at least one electrically conductive line to at least one of the contact pads.
Dependencies are inferred from the claim text.