Socket structure for three-dimensional memory
AssigneeSony Corporation
InventorJun Sumino
Life of this patent
Estimating the term…
Abstract
Socket structures that are configured to use area efficiently, and methods for providing socket regions that use area efficiently, are provided. The staircase type contact area or socket region includes dielectric layers between adjacent planar electrodes that partially cover a portion of a planar electrode that does directly underlie an adjacent planar electrode. The portion of a dielectric layer between adjacent planar electrodes can be sloped, such that it extends from an edge of an overlying planar electrode to a point between the edge of an underlying planar electrode and a point corresponding to an edge of the overlying planar electrode.
Claims11
A memory structure, comprising:
- a plurality of memory arrays configured to be stacked, wherein each of the memory arrays includes a plurality of memory cells;
- a plurality of word lines configured to be coupled to the plurality of the memory cells via a plurality of electrodes;
- a plurality of dielectric layers configured to be located between the electrodes;
- a socket region configured to be located along one side of the memory arrays;
- a plurality of conductors configured to be located between each of the word lines and each of the electrodes.
Dependencies are inferred from the claim text.