1s1r memory cells incorporating a barrier layer

A resistive memory cell, comprising:

• a substrate;
• a first and second electrode material disposed over the substrate;
• a thin film memory element and a thin film selector element disposed between the first and second electrode materials;
• and
• an electrically floating conductive thin film barrier disposed between the memory element and selector element.

A system on chip (SoC), comprising:

• a resistive memory array including a plurality of resistive memory bitcells, each bitcell further including:
• a first and second electrode material disposed over a substrate;
• and
• a thin film memory element and a thin film selector element disposed between the first and second electrode materials;
• an electrically floating conductive thin film barrier disposed between the memory element and selector element, wherein the first and second electrode materials are further coupled to a wordline and a bitline;
• and
• a plurality of MOS transistors disposed over the substrate, one or more of the plurality of transistors electrically coupled to the resistive memory array.

A method of fabricating a resistive memory cell, comprising:

• depositing a first electrode material over a substrate;
• depositing one of a thin film memory element and a thin film selector element over the first electrode material;
• depositing a conductive thin film barrier over the memory or selector element;
• depositing the other of the memory element and the selector element over the barrier;
• and
• depositing a second electrode material over the other of the memory element and the selector element.