Diode structures with controlled injection efficiency for fast switching

A diode device disposed in a semiconductor substrate comprising:

• a heavily doped bottom layer of a first conductivity type supporting a lower buffer layer of the first conductivity type above the heavily doped bottom layer of a first conductivity type;
• an upper buffer layer of the first conductivity type disposed below a top anode layer of a second conductivity type wherein the upper buffer layer is more heavily doped than the first buffer layer to function as an ejection efficiency controlling buffer layer;
• a middle lightly doped buffer layer of the first conductivity type disposed between the upper buffer layer and the lower buffer layer of the first conductivity type;
• a plurality of trench gates wherein each of the trench gates opened from the top surface above the anode layer into a bottom of the upper heavily buffer layer filled with a gate conductive material and padded with a gate dielectic layer and wherein at least two adjacent trench gates surround and insulate a top region of the first conductivity type;
• and
• an anode electrode disposed on the top surface of the semiconductor substrate and is in direct contact with the top anode layer and top region of the first conductivity type.

A diode integrated with an integrated-gate bipolar transistor (IGBT) device in a semiconductor substrate comprising:

• a bottom layer comprises a first layer segment of heavily doped first conductivity type and a second segment of heavily doped second conductivity type wherein the bottom layer supporting a lower buffer layer of the first conductivity type disposed above the bottom layer;
• an upper buffer layer of the first conductivity type disposed below a top anode layer of a second conductivity type wherein the upper buffer layer is more heavily doped than the first buffer layer to function as an ejection efficiency controlling buffer layer;
• a middle lightly doped buffer layer of the first conductivity type disposed between the upper buffer layer and the lower buffer layer of the first conductivity type;
• a plurality of trench gates wherein each of the trench gates opened from the top surface above the anode layer into a bottom of the upper heavily buffer layer filled with a gate conductive material and padded with a gate dielectic layer and wherein at least two adjacent trench gates surround and insulate a top region of the first conductivity type direct in contact with a top anode electrode layer;
• and
• another two adjacent trench gates surround and insulate a region of the top anode layer as an IGBT body region encompassing an IGBT source region of the first conductivity therein and an IGBT planar gate disposed above the IGBT body region and the IGBT source region.