Semiconductor device

A semiconductor device including a trench-gate type field effect transistor configuring a power transistor in a transistor formation region on a main surface of a semiconductor substrate, comprising:

• a first trench formed in the transistor formation region of the semiconductor substrate;
• a first electrode formed in a lower portion inside the first trench;
• a gate electrode for the trench-gate type field effect transistor formed in an upper portion inside the first trench;
• a first insulating film formed between the first electrode and a side wall and a bottom surface of the first trench;
• a second insulating film formed between the gate electrode and the side wall of the first trench;
• a third insulating film formed between the first electrode and the gate electrode;
• a semiconductor region for a source of a first conductivity type formed in a region that is adjacent to the first trench in the semiconductor substrate, a semiconductor region for channel formation of a second conductivity type opposite to the first conductivity type positioned below the semiconductor region for a source, and a semiconductor region for a drain of the first conductivity type positioned below the semiconductor region for channel formation;
• an interlayer insulating film formed on the main surface of the semiconductor substrate;
• a wiring for a source formed on the interlayer insulating film and electrically connected to the semiconductor region for a source;
• a wiring for a gate formed on the interlayer insulating film and electrically connected to the gate electrode;
• and
• a first wiring formed on the interlayer insulating film and electrically connected to the first electrode,
• wherein the first wiring is not connected to the wiring for a source through a conductor, and is not connected to the wiring for a gate through a conductor,
• wherein the wiring for a source is arranged in the transistor formation region in plan view,
• wherein the first wiring is formed on the interlayer insulating film in a periphery of the transistor formation region in plan view,
• wherein the wiring for a gate is formed on the interlayer insulating film in a periphery of the transistor formation region in plan view, and
• wherein the wiring for a gate is arranged between the wiring for a source and the first wiring in plan view.