Shallow-Trench Semi-Super-Junction VDMOS Device and Manufacturing Method Therefor

A manufacturing method of a shallow-trench semi-super-junction Vertical Double-diffused Metal Oxide Semiconductor (VDMOS) device, comprises:

• providing a substrate of a first conduction type;
• forming a first epitaxial layer over the substrate of the first conduction type, wherein the first epitaxial layer has a same conduction type with the substrate of the first conduction type;
• forming a second epitaxial layer over the first epitaxial layer, wherein the second epitaxial layer has a same conduction type with the second epitaxial layer;
• inscribing two trench regions on an upper surface of the second epitaxial layer, wherein the two trench regions extends from the upper surface of the second epitaxial layer to a bottom of the second epitaxial layer and are disposed with an interval,
• forming a third epitaxial layer of a second conduction type in each of the two trench regions, wherein the third epitaxial layers have a conduction type opposite to that of the second epitaxial layer;
• forming a fourth epitaxial layer over the second epitaxial layer, wherein the fourth epitaxial layer has a same conduction type with the second epitaxial layer;
• forming two well regions which are implanted from an upper surface of the fourth epitaxial layer and connected with the two third epitaxial layers in the trench regions, wherein the well regions have a same conduction type with the third epitaxial layers;
• forming a first source region and a second source region of the first conduction type over the two well regions;
• forming a gate region between the first source region and the second source region and over the fourth epitaxial layer;
• and
• forming a drain metal layer under the substrate of the first conduction type;
• forming a gate metal layer over the gate region;
• forming a source metal layer over the first source region and the second source region.