Semiconductor device structure and method for fabricating the same

A semiconductor device structure, comprising:

• a semiconductor substrate;
• a first device and a second device, each of the devices comprising:
• a gate extending in a first direction;
• source/drain regions respectively formed on opposite first and second sides of the gate, wherein a second direction from the source/drain region on the first side to the source/drain region an the second side crosses the first direction;
• dielectric spacers formed respectively on outer sidewalls of the gate on the first side and the second side;
• and
• conductive spacers serving contacts to the source/drain regions and formed respectively on outer sidewalls of the respective gate spacers,
• wherein the first device and the second device are adjacent to each other in the first direction, their respective gates align to each other and extend in a substantially straight line along the first direction, their respective dielectric spacers align to each other and extend in a substantially straight line along the first direction, and their respective conductive spacers align to each other and extend in a substantially straight line along the first direction,
• wherein an end surface of the gate of the first device facing the second device and end surfaces of the conductive spacers of the first device facing the second device are substantially flush with each other, and
• wherein the semiconductor device structure further comprises inter-device electrical isolation provided between the first device and the second device.

A semiconductor device structure, comprising:

• a semiconductor substrate;
• a first device and a second device, each of the devices comprising:
• a gate having opposite first and second sidewalls and also opposite third and fourth sidewalls;
• source/drain regions respectively formed on opposite sides of the gate;
• dielectric spacers formed respectively on the first and second sidewalls of the gate;
• conductive spacers serving contacts to the source/drain regions and formed respectively on sidewalls of the respective dielectric spacers facing away from the gate,
• wherein the first device and the second device face each other with one of their respective third or fourth sidewalls,
• wherein the dielectric spacer of the first device on the first sidewall thereof and the dielectric spacer of the second device on the first sidewall thereof extend only on a plane defined by the respective first sidewalls of the first and second devices, and the dielectric spacer of the first device on the second sidewall thereof and the dielectric spacer of the second device on the second sidewall thereof extend only on a plane defined by the respective second sidewalls of the first and second devices, and
• wherein the semiconductor device structure further comprises inter-device electrical isolation between the first device and the second device.