Fabrication of vertical field effect transistor structure with controlled gate length

A vertical fin field effect transistor (finFET), comprising;

• one or more vertical fins formed on a substrate;
• a bottom spacer on the substrate and adjacent the sidewall of at least one of the one or more vertical fins;
• a gate structure on at least a portion of the sidewalls of at least one of the one or more vertical fins, where the gate structure has a gate length;
• an oxide layer on at least a portion of at least one of the one or more vertical fins;
• and
• a SiBCN layer on the oxide layer.

A vertical fin field effect transistor (finFET), comprising;

• one or more vertical fins formed on a substrate;
• a doped region in the substrate located below at least one of the one or more vertical fins;
• a bottom spacer on the substrate and adjacent the sidewall of at least one of the one or more vertical fins;
• a high-k dielectric layer on at least a portion of the bottom spacer and at least a portion of the sidewalls of at least one of the one or more vertical fins;
• a work function layer on at least a portion of the high-k dielectric layer;
• a gate metal layer on at least a portion of the work function layer;
• a gauge layer on at least a portion of the gate metal layer;
• and
• an oxide layer on at least a portion of at least one of the one or more vertical fins and on the gauge layer.