Nanowire transistor and method for fabricating the same
AssigneeUnited Microelectronics Corp.
InventorYu-Cheng Tung
Life of this patent
Estimating the term…
Abstract
A method for fabricating a nanowire transistor is disclosed. First, a substrate is provided, and a stack structure is formed on the substrate, in which the stack structure includes a first semiconductor layer and a second semiconductor layer and the first semiconductor layer and the second semiconductor layer are made of different material. Next, a hard mask is formed on the stack structure and a first spacer adjacent to the hard mask, part of the stack structure is removed; a second spacer is formed adjacent to the first spacer and the stack structure; and a source/drain structure is formed adjacent to two sides of the second spacer.
Claims20
A method for fabricating a nanowire transistor, comprising:
- providing a substrate;
- forming a stack structure on the substrate, wherein the stack structure comprises a first semiconductor layer and a second semiconductor layer and the first semiconductor layer and the second semiconductor layer comprise different material;
- forming a hard mask on the stack structure and a first spacer adjacent to the hard mask;
- removing part of the stack structure;
- forming a second spacer adjacent to the first spacer and the stack structure, wherein the top surfaces of the first spacer and the second spacer are coplanar;
- and
- forming a source/drain structure adjacent to two sides of the second spacer.
A nanowire transistor, comprising:
- a substrate;
- a nanowire channel layer on the substrate;
- a gate structure on and around the nanowire channel layer;
- a first spacer on the sidewalls of the gate structure;
- a second spacer on the sidewalls of the first spacer and the nanowire channel layer, wherein the top surfaces of the first spacer and the second spacer are coplanar;
- and
- a source/drain structure adjacent to two sides of the second spacer.
A nanowire transistor, comprising:
- a substrate;
- a nanowire channel layer on the substrate;
- a gate structure on the nanowire channel layer;
- a source/drain structure adjacent to two sides of the gate structure and contacting the substrate directly, wherein the source/drain structure comprises metal and a top surface of the source/drain structure is lower than a top surface of the gate structure;
- and
- a spacer between the nanowire channel layer and the source/drain structure.
Dependencies are inferred from the claim text.