Semiconductor structure including a trench capping layer

A semiconductor structure, comprising:

• a trench isolation structure positioned in a semiconductor substrate, said trench isolation structure comprising a first insulating material;
• a trench capping layer covering at least a portion of an upper surface of said trench isolation structure, said trench capping layer comprising a second insulating material that is different from said first insulating material;
• a gate structure comprising a gate insulation layer and a gate electrode positioned above said gate insulation layer, said gate structure having a first portion that is positioned above said trench capping layer and a second portion that is positioned above an active region of a semiconductor material layer of said semiconductor substrate;
• and
• a sidewall spacer positioned adjacent to said gate structure, wherein said sidewall spacer covers a sidewall surface of said gate insulation layer and a portion of an upper surface of said trench capping layer.

A semiconductor structure, comprising:

• a trench isolation structure positioned in a silicon-on-insulator (SOI) substrate, said trench isolation structure comprising a first insulating material;
• a trench capping layer covering at least a portion of an upper surface of said trench isolation structure, wherein said trench capping layer at least partially separates a first active region of a semiconductor material layer of said SOI substrate from a second active region of said semiconductor material layer and comprises a second insulating material that is different from said first insulating material;
• a gate structure of a field effect transistor, said gate structure comprising a high-k gate insulation layer positioned above and extending across a first portion of an upper surface of said trench capping layer and a first portion of an upper surface of said semiconductor material layer, a gate electrode positioned above said gate insulation layer, and a work-function adjustment metal layer positioned between said gate insulation layer and said gate electrode;
• a sidewall spacer positioned adjacent to said gate structure, wherein said sidewall spacer covers a sidewall surface of said gate insulation layer and a second portion of said upper surface of said trench capping layer;
• a raised epitaxial source region positioned above a second portion of said upper surface of said semiconductor material layer;
• a raised epitaxial drain region positioned above a third portion of said upper surface of said semiconductor material layer;
• an interlayer dielectric covering said gate structure and said raised epitaxial source and drain regions;
• a source contact element extending through said interlayer dielectric and electrically contacting said raised epitaxial source region;
• and
• a drain contact element extending through said interlayer dielectric and electrically contacting said raised epitaxial drain region.