Thermal insulation for three-dimensional memory arrays

A three dimensional memory array, comprising:

• a first layer that comprises a first memory cell and a first electrode, wherein the first memory cell comprises a chalcogenide material and is coupled to the first electrode;
• a second layer that comprises a second memory cell and a second electrode, wherein the second memory cell comprises the chalcogenide material and is coupled to the second electrode, and wherein the second layer is substantially parallel to the first layer;
• a plurality of insulating layers positioned between the first layer and the second layer, wherein the plurality of insulating layers are substantially parallel to the first and second layers, and wherein a first insulating layer and a second insulating layer of the plurality each comprise an electrical insulator;
• a third electrode positioned substantially perpendicular to the first and second layers, wherein the third electrode is adjacent to the first and second memory cells;
• and
• a selection component coupled to the third electrode.

A method of forming a three dimensional memory array, comprising:

• forming a stack comprising a set of conductive layers, wherein each conductive layer of the set is separated from an adjacent conductive layer of the set by a thermally insulating region, the thermally insulating region having a thermal resistance greater than that of the adjacent conductive layer;
• forming a set of insulating layers within each thermally insulating region, wherein the set of insulating layers comprises at least two layers that comprise electrically insulating material;
• forming a via through the stack, wherein at least a portion of the via passes through each conductive layer of the set of conductive layers;
• forming a recess in at least one conductive layer of the set of conductive layers, wherein the recess is adjacent the via;
• and
• forming a memory cell within the recess.