High aperture ratio display by introducing transparent storage capacitor and via hole

A method of manufacturing an apparatus, the apparatus having a TFT region and a storage capacitor region adjacent to the TFT region, the method comprising:

• providing a substrate in the TFT and the storage capacitor region;
• forming a first metal layer on the substrate in the TFT region;
• forming a first dielectric layer on the first metal layer;
• forming an oxide semiconductor layer in the storage capacitor region and on the first dielectric layer in the TFT region, wherein the oxide semiconductor layer in the TFT region has a channel region between a source region and a drain region;
• forming a second metal layer on the oxide semiconductor layer, the second metal layer in contact with the source region and the drain region, and the second metal layer in contact with a portion of the oxide semiconductor layer in the storage capacitor region;
• forming a second dielectric layer on the second metal layer and the oxide semiconductor layer in the TFT region;
• forming a transparent conductive layer over the oxide semiconductor layer in the storage capacitor region, the transparent conductive layer at least partially overlapping with the oxide semiconductor layer in the storage capacitor region;
• and
• applying, after any operation subsequent to forming the oxide semiconductor layer, a resistance lowering process to the oxide semiconductor layer in the storage capacitor region so that the oxide semiconductor layer in the storage capacitor region has a lower electrical resistance than the oxide semiconductor layer in the channel region.

A method of manufacturing an apparatus, the apparatus having a TFT region, a storage capacitor region adjacent to the TFT region, and a common electrode region adjacent to the storage capacitor region, the method comprising:

• providing a substrate in the TFT, the storage capacitor, and the common electrode region;
• forming a first metal layer on the substrate in the TFT region;
• forming a first dielectric layer on the first metal layer;
• forming an oxide semiconductor layer in the storage capacitor region and the common electrode region and on the first dielectric layer in the TFT region, wherein the oxide semiconductor layer in the TFT region has a channel region between a source region and a drain region;
• forming a second metal layer on the oxide semiconductor layer, the second metal layer in contact with the source region and the drain region;
• forming a second dielectric layer on the second metal layer and the oxide semiconductor layer in the TFT region;
• forming a transparent conductive layer over the oxide semiconductor layer in the storage capacitor region, the transparent conductive layer at least partially overlapping with the oxide semiconductor layer in the storage capacitor region;
• and
• applying, after any operation subsequent to forming the oxide semiconductor layer, a resistance lowering process to the oxide semiconductor layer in the storage capacitor region and the common electrode region so that the oxide semiconductor layer in the storage capacitor region and the common electrode region has a lower electrical resistance than the oxide semiconductor layer in the TFT region.