Semiconductor memory device and fabrication method thereof

A semiconductor memory device, comprising:

• a substrate;
• a plurality of stacked structures formed on the substrate, wherein the stacked structures include a tunneling dielectric layer and a floating gate layer sequentially formed on the substrate, each stacked structure is parallel and evenly spaced to each other, the spacing between the adjacent stacked structures forms a plurality of first trenches, the first trenches extend into the inner of the substrate, bottom of the first trenches exposes the substrate, and side walls of the first trenches expose the substrate, the tunneling dielectric layer, and the floating gate layer;
• a first liner layer formed on inner walls of the first trenches, wherein a height of the first liner layer is higher than a height of the tunneling dielectric layer and lower than a height of the floating gate layer;
• a first dielectric layer formed on the first liner layer, wherein a height of the first dielectric layer is lower than the height of the tunneling dielectric layer;
• a second liner layer formed on the first liner layer and the first dielectric layer;
• a plurality of air gaps formed in the first trenches and extended along a direction of the first trenches, wherein side walls and bottom of the air gaps expose the second liner layer;
• a second dielectric layer covering surfaces of the floating gate layer and the air gaps;
• a control gate layer formed on the second dielectric layer;
• a plurality of fourth trenches formed in the control gate layer and the floating gate layer, wherein an extension direction of each fourth trench is parallel to each other and perpendicular to an extension direction of each first trench, and bottom of the fourth trenches exposes the surfaces of the tunneling dielectric layer and the air gaps;
• and
• a third dielectric layer formed in the fourth trenches to sufficiently fill the fourth trenches.