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US 2017/0287921 A1Published application
Method of improving localized wafer shape changes
AssigneeMacronix International Co., Ltd.
InventorsCHI-PIN LU, PEI-CI JHANG, FU-HSING CHOU, CHIH-HSIUNG LEE
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Abstract
A method of manufacturing an integrated circuit including forming trenches into the surface of a crystalline wafer and the trenches extending along a <100> lattice direction is disclosed. Such wafer can experience less deformation due to less stress induced when the trenches are filled using a spin-on dielectric material. Thus, the overlay issue caused by wafer shape change is resolved.
Claims20
A method of manufacturing an integrated circuit, comprising:
- providing a crystalline wafer having a surface in a (100) lattice plane;
- forming an array of dies on the surface of the wafer, each die having memory array regions and peripheral circuit regions;
- forming a first plurality of trenches into the surface in the memory array regions, the trenches in the first plurality extending along a <100> lattice direction;
- and
- forming a second plurality of trenches into the surface in the peripheral circuit regions, the trenches in the second plurality extending along the <100> lattice direction.
2 more elements
A method of manufacturing an integrated circuit, comprising:
- providing a crystalline wafer having a surface normal to a <100> lattice direction;
- forming an array of die on the surface of the wafer, the die having memory array regions and peripheral circuit regions;
- forming a first plurality of trenches into the surface in the memory array regions and a second plurality of trenches into the surface in the peripheral circuit regions, the trenches in the first and second pluralities extending along said <100> lattice direction;
- and
- spin-coating an insulating material to fill the trenches in the first and second pluralities, the wafer having a bow height.
2 more elements
A semiconductor device comprising:
- a substrate having an oxygen concentration ranging from 7 to 10 parts per million atoms (ppma) and a denuded zone substantially greater than 5 μm;
- a first dielectric formed over the substrate and a first semiconductor formed over the first dielectric;
- a first plurality of isolation structures in the substrate including a first insulating material in a first plurality of trenches extending along a <100> lattice direction in memory array regions, wherein the first plurality of trenches has a trench width W1;
- and
- a second plurality of isolation structures in the substrate including a second insulating material in a second plurality of trenches extending along the <100> lattice direction in peripheral circuit regions, wherein the second plurality of trenches has a trench width W2 and the trench width W1 is narrower than the trench width W2.
2 more elements
Dependencies are inferred from the claim text.