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US 2017/0287919 A1Published application
Single event upset (seu) mitigation for finfet technology using fin topology
AssigneeXilinx, Inc.
InventorPierre Maillard
Life of this patent
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Abstract
Front end circuits that include a FinFET transistor are described herein. In one example, the front end circuit has a FinFET transistor that includes a channel region wrapped by a metal gate, the channel region connecting a source and drain fins. At least one of the source and drain fins have a height (HTOT) and a width W. The height (HTOT) is greater than an optimal height (HOPT), wherein the height HOPT is a height that would optimize speed of a FinFET transistor having the width W.
Claims17
A front end circuit comprising:
- a FinFET transistor comprising:
- a metal gate;
- a source fin;
- a drain fin;
- a channel region wrapped by the metal gate, the channel region connecting the source and drain fins;
- wherein at least one of the source and drain fins have a height (HTOT) and a width W, the height (HTOT) is greater than an optimal height (HOPT), wherein the height HOPT is a height that would optimize speed of a FinFET transistor having the width W.
3 more elements
A front end circuit comprising:
- a memory structure comprising:
- at least one FinFET transistor comprising:
- a metal gate;
- a source fin;
- a drain fin;
- a channel region wrapped by the metal gate, the channel region connecting the source and drain fins;
- wherein at least one of the source and drain fins have a height (HTOT) and a width W, the height (HTOT) is greater than an optimal height (HOPT), wherein the height HOPT is a height that would optimize speed of a FinFET transistor having the width W.
4 more elements
An electronic circuit comprising:
- a front end circuit comprising:
- a SRAM memory structure comprising a plurality of FinFET transistors, wherein at least a first FinFET transistor of the plurality of FinFET transistors comprises:
- a metal gate;
- a source fin;
- a drain fin;
- a channel region wrapped by the metal gate, the channel region connecting the source and drain fins;
- wherein at least one of the source and drain fins have a height (HTOT) and a width W, the height (HTOT) is greater than an optimal height (HOPT), wherein the height HOPT is a height that would optimize speed of a FinFET transistor having the width W.
4 more elements
Dependencies are inferred from the claim text.