Layout method and semiconductor device

A semiconductor device, comprising:

• a circuit region and a dummy region, the dummy region including a first dummy region and a second dummy region, and the circuit region including a first circuit region opposing the first dummy region and a second circuit region spaced apart from the first dummy region,
• circuit active fin patterns in the circuit region;
• dummy active fin patterns in the dummy region at a same pitch as a pitch of the circuit active fin patterns;
• circuit gate lines in the circuit region;
• and
• dummy gate lines in the dummy region at a same pitch as a pitch of the circuit gate lines,
• wherein a density of the dummy active fin patterns in the first dummy region is different from a density of the circuit active fin patterns in the first circuit region, and
• wherein a density of the dummy active fin patterns in the second dummy region is different from a density of the dummy active fin patterns in the first dummy region.

A semiconductor device, comprising:

• a circuit region and a dummy region adjacent to each other;
• circuit active fin patterns in the circuit region and having a linear shape extended in a first direction;
• dummy active fin patterns in the dummy region and having a linear shape extended in the first direction, the dummy active fin patterns including first-side fin patterns having end portions opposing end portions of the circuit active fin patterns;
• circuit gate lines in the circuit region and intersecting the circuit active fin patterns;
• and
• dummy gate lines in the dummy region and having end portions opposing end portions of the circuit gate lines,
• wherein sides of the circuit active fin patterns and sides of the first-side fin patterns are aligned with each other, and
• wherein sides of the circuit gate lines and sides of the dummy gate lines are aligned with each other.