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US 2017/0287903 A1Published application
Variable snubber for mosfet application
AssigneeAlpha and Omega Semiconductor Incorporated
InventorsSik Lui, Ji Pan
Life of this patent
Estimating the term…
Abstract
Aspects of the present disclosure describe MOSFET devices that have snubber circuits. The snubber circuits comprise one or more resistors with a dynamically controllable resistance that is controlled by changes to a gate and/or drain potentials of the one or more MOSFET structures during switching events.
Claims20
A transistor device, comprising:
- one or more gated structures formed in a semiconductor substrate, wherein the one or more gated structures comprise one or more field effect transistor structures each having a gate electrode;
- a snubber circuit connected in parallel with the one or more gated structures, wherein the snubber circuit includes one or more three-terminal resistors with a dynamically controllable resistance controlled by changes to a gate potential of the one or more gated structures during a switching event.
A transistor device, comprising:
- one or more gated structures formed in a semiconductor substrate, wherein the one or more gated structures comprise one or more field effect transistor structures each having a gate electrode;
- one or more three-terminal resistors with a dynamically controllable resistance controlled by changes to a gate potential of the one or more gated structures during a switching event, wherein the one or more three-terminal resistors with a dynamically controllable resistance includes polysilicon disposed above the gate electrode of one or more of the field effect transistor structures.
A transistor device, comprising:
- one or more gated structures formed in a semiconductor substrate, wherein the one or more gated structures comprise one or more field effect transistor structures each having a gate electrode;
- a snubber circuit connected in parallel with the one or more gated structures, wherein the snubber circuit includes one or more three-terminal resistors with a dynamically controllable resistance controlled by changes to a drain potential of the one or more field effect transistor structures during a switching event.
A transistor device, comprising:
- one or more gated structures formed in a semiconductor substrate, wherein the one or more gated structures comprise one or more field effect transistor structures each having a gate electrode;
- one or more three-terminal resistors with a dynamically controllable resistance controlled by changes to a drain potential of the one or more field effect transistor structures during a switching event, wherein the one or more three-terminal resistors with a dynamically controllable resistance includes polysilicon disposed above the semiconductor substrate in a termination region of the transistor device, wherein the semiconductor substrate in the termination region is maintained at the drain potential of the one or more field effect transistor structures.
Dependencies are inferred from the claim text.