Semiconductor structure including a transistor including a gate electrode region provided in a substrate and method for the formation thereof

A method, comprising:

• providing a semiconductor structure comprising a bulk semiconductor substrate, an electrically insulating layer over said bulk semiconductor substrate and an active layer of semiconductor material over said electrically insulating layer, said bulk semiconductor substrate comprising a bulk semiconductor material;
• forming a first transistor, the formation of said first transistor comprising:
• forming a gate electrode region in a first portion of said bulk semiconductor material comprising said bulk semiconductor substrate, said gate electrode region having a first type of doping, at least a portion of said gate electrode region being arranged directly below said electrically insulating layer;
• and
• forming an active region of said first transistor in said active layer of semiconductor material, said active region of said first transistor comprising a source region, a channel region and a drain region of said first transistor, wherein at least said channel region of said first transistor is provided above said at least a portion of said gate electrode region that is arranged directly below said electrically insulating layer;
• wherein no gate electrode of said first transistor is formed on a side of said active layer of semiconductor material opposite said bulk semiconductor substrate.

A semiconductor structure, comprising:

• a bulk semiconductor substrate comprising a bulk semiconductor material, an electrically insulating layer over said bulk semiconductor substrate and an active layer of semiconductor material over said electrically insulating layer;
• and
• a transistor, comprising:
• an active region provided in said active layer of semiconductor material, said active region comprising a source region, a channel region and a drain region;
• a gate electrode region provided in a first portion of said bulk semiconductor material comprising said bulk semiconductor substrate and having a first type of doping, at least a portion of said gate electrode region being arranged directly below a portion of said electrically insulating layer below said channel region;
• an isolation junction region formed in said bulk semiconductor material comprising said bulk semiconductor substrate, said isolation junction region having a second type of doping opposite said first type of doping and separating said gate electrode region from a second portion of said bulk semiconductor substrate surrounding said gate electrode region and having said first type of doping, wherein a PN-transition is formed between said gate electrode region and said isolation junction region, and wherein a PN-transition is formed between said isolation junction region and said second portion of said bulk semiconductor material comprising said bulk semiconductor substrate surrounding said gate electrode region;
• and
• an interlayer dielectric over said channel region on a side of said active layer of semiconductor material opposite said bulk semiconductor substrate.