Three dimensional fully molded power electronics module having a plurality of spacers for high power applications

A fully molded power electronic module that includes a power chip and a second chip that operates at a lower power than the power chip, comprising:

• a first direct bonded copper (DBC) substrate;
• a second DBC substrate oppositely disposed from the first DBC substrate;
• a plurality of first solder blocks disposed on an inner surface of the first DBC substrate;
• a plurality of first electrically non-conductive blocks disposed on the inner surface of the first DBC substrate;
• a plurality of second solder blocks disposed on an inner surface of the second DBC substrate;
• a plurality of second electrically non-conductive blocks disposed on the inner surface of the second DBC substrate;
• a power chip having a top surface that contacts one of the first solder blocks and a bottom surface that contacts one of the second solder blocks;
• a second chip having a top surface that faces one of the first electrically non-conductive blocks and a bottom surface that contacts one of the second solder blocks;
• and
• at least four spacers spaced around a perimeter of the fully molded power electronic package each having a first end that contacts one of the first electrically non-conductive blocks and a second end that contacts one of the second electrically non-conductive blocks.

A method of fabricating a power electronic module that encloses a plurality of chips with different heights, comprising:

• determining, by analyzing thermal properties the chips, a thickness of a first solder block that contacts a top surface of the chips and connects the chips with a first substrate, and a thickness of a second solder block that contacts a bottom surface of the chips and connects the chips with a second substrate, such that heat generated by the chips is dissipated through the first and second substrates;
• calculating a total height by adding the thickness of the first solder block with a thickness of the chips and the thickness of the second solder block;
• determining, a total volume of solder blocks including the first solder block, the second solder block and a plurality of third solder blocks each directly contacts the first substrate and the second substrate;
• forming, based on the total volume of solder blocks, a plurality of first passivation regions on the first substrate and a plurality of second passivation regions on the second substrate, wherein the first and second passivation regions are not solderable;
• mounting, on the first passivation regions of the first substrate, at least four spacers that have a height equal to the total height minus a height of the first passivation regions and a height of the second passivation regions;
• and
• pressing the first substrate against the second substrate until the at least four spacers contact the second passivation regions of the second substrate.