Stacked chip package structure and manufacturing method thereof

A manufacturing method of a stacked chip package structure, comprising:

• disposing a first chip on a carrier, wherein the first chip has a first active surface and a plurality of first pads disposed on the first active surface;
• disposing a second chip on the first chip, wherein the second chip exposes the first pads and has a second active surface and a plurality of second pads disposed on the second active surface;
• forming a plurality of first stud bumps on the first pads;
• forming a plurality of pillar bumps on the second pads;
• encapsulating the first chip and the second chip by an encapsulant, wherein the encapsulant exposes a top surface of each of the pillar bumps;
• forming a plurality of first vias by a laser process, wherein the first vias penetrate the encapsulant and expose the first stud bumps;
• forming a conductive layer in the first vias to form a plurality of first conductive vias;
• and
• removing the carrier.