3d integrated circuit device
AssigneeMonolithic 3D Inc.
InventorsZvi Or-Bach, Deepak C. Sekar, Brian Cronquist
Life of this patent
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Abstract
A 3D integrated circuit device, including: a first transistor; a second transistor; and a third transistor, where the third transistor is overlaying the second transistor and the second transistor is overlaying the first transistor, where the first transistor controls the supply of a ground or a power signal to the third transistor, and where the first transistor, the second transistor and the third transistor are aligned to each other with less than 100 nm misalignment.
Claims20
A 3D integrated circuit device, comprising:
- a first transistor;
- a second transistor;
- and
- a third transistor,
- wherein said third transistor is overlaying said second transistor and said second transistor is overlaying said first transistor,
- wherein said first transistor controls the supply of a ground or a power signal to said third transistor, and
- wherein said first transistor, said second transistor and said third transistor are aligned to each other with less than 100 nm misalignment.
A 3D integrated circuit device, comprising:
- a first transistor;
- a second transistor, said second transistor has a second transistor gate dielectric;
- and
- a third transistor, said third transistor has a third transistor gate dielectric,
- wherein said third transistor is overlaying said second transistor and said second transistor is overlaying said first transistor,
- wherein said second transistor and said third transistor are junction-less transistors,
- wherein said second transistor gate dielectric and said third transistor gate dielectric are part of the same layer, and
- wherein said first transistor, said second transistor and said third transistor are aligned to each other with less than 100 nm misalignment.
A 3D integrated circuit device, comprising:
- a first transistor;
- a second transistor;
- and
- a third transistor,
- wherein said third transistor is overlaying said second transistor and said second transistor is overlaying said first transistor,
- wherein said second transistor and said third transistor each have a first gate and a second gate,
- wherein said second transistor first gate is connected to said third transistor first gate,
- wherein said first gate is not connected to said second gate, and
- wherein said first transistor, said second transistor and said third transistor are aligned to each other with less than 100 nm misalignment.
Dependencies are inferred from the claim text.