Multi-chip package structure manufacturing process and wafer level chip package structure manufacturing process

A wafer level chip package manufacturing process, comprising:

• providing a wafer, the wafer comprising a plurality of first chips arranged in an array and a circuit layer disposed on the first chips, wherein each of the first chips has a chip bonding region, a plurality of first inner pads located in the chip bonding region and a plurality of first outer pads located outside the chip bonding region, the circuit layer comprises a plurality of insulating layers and at least one metal layer disposed between the insulating layers, the insulating layers have at least one groove, the at least one groove is disposed between the first inner pads and the first outer pads, and the at least one groove surrounds the first inner pads, wherein partial regions of the at least one groove sink towards positions corresponding to spaces between the first outer pads so that an outer profile of the at least one groove appears as a profile staggered with straight lines and arcs;
• forming a plurality of first conductive bumps on the first outer pads;
• providing a plurality of second chips, each of the second chips having a plurality of second pads, and the second pads being formed with a plurality of second conductive bumps thereon;
• flipping the second chips on the chip bonding regions, so that the second conductive bumps are located between the first inner pads and the second pads, and each of the first inner pads is electrically connected with the corresponding second pad through the corresponding second conductive bump;
• and
• forming an underfill between the first chips and the second chips, so as to cover the second conductive bumps.

A multi-chip package structure manufacturing process, comprising:

• providing a first chip, wherein the first chips has a chip bonding region, a plurality of first inner pads located in the chip bonding region and a plurality of first outer pads located outside the chip bonding region;
• disposing a circuit layer on the first chip, the circuit layer comprises a plurality of insulating layers and at least one metal layer disposed between the insulating layers, the insulating layers have at least one groove, the at least one groove is disposed between the first inner pads and the first outer pads, and the at least one groove surrounds the first inner pads, wherein partial regions of the at least one groove sink towards positions corresponding to spaces between the first outer pads so that an outer profile of the at least one groove appears as a profile staggered with straight lines and arcs;
• forming a plurality of first conductive bumps on the first outer pads;
• providing a second chip having a plurality of second pads, and the second pads being formed with a plurality of second conductive bumps thereon;
• flipping the second chip on the chip bonding region, so that the second conductive bumps are located between the first inner pads and the second pads, and each of the first inner pads is electrically connected with the corresponding second pad through the corresponding second conductive bump;
• and
• forming an underfill between the first chip and the second chip, so as to cover the second conductive bumps.